Conventional first-in, first-out (FIFO) memories are equipped with status flag generators that generate status flags responsive to predetermined portions of the capacity of the memory being used. These flags, for example, may include an EMPTY flag to indicate that the associated FIFO memory is empty, a FULL flag to indicate that the FIFO memory is full, and other flags to indicate intermediate conditions. The EMPTY flag is often used to disable further reading of data from the FIFO memory, and the FULL flag is often used to disable further writing of data into the FIFO memory.
In the application of this invention, the FIFO is designed to use an up/down counter to determine the difference between the values stored in a write counter of the FIFO memory and in a read counter thereof. The write counter indicates the address of the FIFO memory into which data is to be written, and the read counter indicates the address in the FIFO from which data is to be read. The up/down counter keeps a record of the difference between the write counter and the read counter, thereby recording the amount of capacity being used in the FIFO. This up/down counter is used to generate any of a selected number of status flags.
A traditional method of using the output of the up/down counter to generate status flags is to decode the outputs through several stages of decoding gates. As the size of the up/down counter increases, the delay experienced in decoding the state of the up/down counter increases. A need has therefore arisen for a flag generator that can generate a status flag from an up/down counter with less delay.